The technology of producing semiconductor devices has been continually pressured to increase effective device densities in order to remain cost competitive. As a result, Very Large Scale Integration (VLSI) and Ultra Large Scale Integration (ULSI) technologies have entered the sub-micron realm of structural dimension and now are approaching physical limits in the nanometer feature size range. In the foreseeable future, absolute atomic physical limits will be reached in the conventional two-dimensional approach to semiconductor device design. Traditionally, dynamic random access memory (DRAM) designers have faced the severest of challenges in advancing technologies. For example, designers of 64K DRAMs were perplexed to learn that a practical physical limit to charge capacity of storage capacitors had already been reached due to the minimum charge necessary to sense signals in the presence of environmental or particulate radiation inherently present in fabrication materials. Storage capacitors in the range of 50 femtofarads are now considered to be a physical limit. From a practical view, this limitation prevented the scaling of DRAM capacitors. Reduction of the surface area of a semiconductor substrate utilized by the storage capacitor has also been severely restricted. Due to decreases in the thickness of capacitor materials, existing 1 Megabit (1 Mbit) DRAM technologies utilize a planar device in circuit design. Beginning with 4M bit DRAMs, the world of three-dimensional design has been explored to the extent that the simple single device/capacitor memory cell has been altered to provide the capacitor in a vertical dimension. In such designs the capacitor has been formed in a trench in the surface of the semiconductor substrate. In yet denser designs, other forms of capacitor design are proposed, such as stacking the capacitor above the transfer device.
The progress of DRAM technology, which in many ways drives micro-electronics technology, is thus currently limited in significant part by the difficulty of fabricating storage capacitors with sufficient capacitance within decreasing area on the chip. The DRAM world is currently divided between two paths, with some manufacturers pursuing trench capacitors built into the crystalline silicon wafer, and other manufacturers pursuing stacked capacitors in which the capacitor is fabricated on top of the wafer surface. The use of a stacked capacitor permits a variety of new process options, for example, in the choice of electrode material (polysilicon, silicide, etc.). In the case of the trench capacitor, its extendibility is in doubt since it is extremely difficult to etch about 0.15-0.25 micrometer wide trenches well over 10 micrometers deep, as well as to then fabricate ultrathin dielectric layers on the trench surface, fill the trench, etc.
Various attempts have been made to fabricate capacitors having a larger surface area than conventional capacitors. Tsubouchi et al. in U.S. Pat. No. 4,853,348 discloses a capacitor comprising a capacitor hole formed in a p type semiconductor substrate and an n type semiconductor region provided along the capacitor hole so that the pn junction area therebetween is increased and the capacitance is made large.
G. C. Schwartz and P. M. Schaible, J. Vac. Sci. & Technol. 16: 410 (1979) disclose the spontaneous reactive ion etching in chlorine of n-doped silicon without sidewall passivation. The spontaneous etching produces a structure having lateral fins extending from an etched vertical trench if the n-doped silicon extends laterally away from the vertical trench as the vertical trench is etched using chlorine.
This lateral fin formation in the presence of chlorine is also referred to as "blooming" in Lai et al., U.S. Pat. No. 4,475,982, but the Lai et al. Patent is directed to a method of etching which prevents lateral etching or blooming in heavily doped semiconductor regions.
K. Nakamura in Japanese Patent Application Publication No. JP 60-173871, published Sep. 7, 1985, discloses a semiconductor memory device manufactured by forming a groove and several projections from the groove in a semiconductor substrate to increase the surface area of the groove.
M. Nakamae in Japanese Patent Application Publication No. JP 60-176265, published Sep. 10, 1985, discloses a semiconductor memory device having large capacitance which is fabricated by directionally dry etching a small hole in the main surface of a semiconductor substrate. The silicon substrate is then doped and directional dry etching is used to etch sideways from the small hole to form a buried cavity having a width wider than the small hole.
Despite the fabrication of these various capacitor structures, a need continues to exist in the art for a capacitor having a large surface area so that the capacitor's capacitance is increased, without increasing the area occupied by the capacitor structure on or in a silicon substrate.